1. Field of the Invention
This invention relates to a low profile package which is adapted for use with semiconductor wafers and/or with one or more semiconductor chips. It is suitable for use in an operating environment where efficient heat dissipation from the package is essential.
2. Prior Art
Wafer scale integration involves forming an integrated circuit utilizing an entire semiconductor wafer. Typically a semiconductor wafer may have a diameter of up to eight inches or more. The wafer is not diced to form chips, but rather is utilized in its entirety to form the integrated circuit. A wafer containing such an integrated circuit must be protected in its operating environment against contamination, as well as against mechanical and thermal stress. A package for protecting and supporting such a wafer must also provide an efficient method for cooling the wafer and must occupy a minimal amount of space to allow it to be used in a crowded environment, e.g. in a compact chassis housing multiple electronic components.
Several approaches have been used to provide such packages. For example, in U.S. Pat. No. 4,603,374 entitled "Packaging Module for a Semiconductor Wafer" and assigned to Motorola, Inc., the wafer is supported on thermally conductive elastomeric pads and is situated under a printed circuit board. The printed circuit board is equipped with electrically conductive plastic pads which engage contact pads on the periphery of the wafer to create electrical contact between wafer and circuit board. U.S. Pat. No. 4,555,024, entitled "Packaging Unit for Semiconductor Wafers" and assigned to Wacker-Chemie GmbH, discloses spring tongues which are used in conjunction with retention cones on the inner surface of the package lid to hold the wafer in place. U.S. Pat. No. 4,706,955, entitled "Package for Hermetically Sealing Electronic Circuits", discloses a hermetic seal for a semiconductor wafer package. As shown in FIG. 1, this seal consists of a base 114 supporting the electronic device 112, to which is attached a sealing ring 142 surrounding the device. Signal leads 116 extend under this sealing ring 142. A flange 148 is bonded to the sealing ring 142, and the gap between flange 148 and lid 154 is filled with solder 156 to provide a hermetic seal. U.S. Pat. No. 4,000,509, entitled "High Density Air Cooled Wafer Package Having Improved Thermal Dissipation", discloses a package in which electrical connections are made around the periphery of the wafer. In this package, the wafer is forced against a heat sink through deformation of springlike elements; thermal grease is used between wafer and heat sink. U.S. Pat. No. 3,908,155, entitled "Wafer Circuit Package", discloses a package wherein wafers are stacked and electrical interconnections are made using tuning fork type connectors.
All these prior art devices provide electrical connections to points along the periphery of the wafer. This tends to result in large differences in electrical path lengths between the exterior of the package and different areas of the wafer. Several of the prior art devices utilize structural elements, e.g. spring tongues, which increase the bulk of the package.